Embedded Design and Virtual Platform Solutions

System Verification

The exponential increasing complexity of embedded hardware and software (especially with OSes such as Linux and Android), along with rapid product development cycles, requires new approaches for verification.  Tools and techniques such as hardware verification languages, virtual platforms, and HW/SW co-verification can greatly improve productivity.

Posedge Software is an active member of Cadence Verification Alliance and OVPWorld.org, and has expertise in the C/C++/SystemC, Verilog, Cadence e, and other languages, and provides consulting services in a number of areas including:

  1. Modeling and Simulation
  2. Testbench Design
  3. HW/SW Co-verification
  4. System-level Verification

Modeling and Simulation

Hardware Verification typically involves creating models of processors, peripherals, and other devices to model the behavior of the device.  These may be RTL models written in Verilog, or increasingly higher-level models written in C or SystemC using TLM2 interface standard.  These models are used to interface with, or compare against the device-under-test (DUT).  Designing of these models at the proper abstraction level is critical to meeting the performance requirements of the veriifcation platform.

Testbench Design

Traditionally, testbenches were written in Verilog/VHDL, and performed a number of directed tests.  As complexity has increased, new techniques such as constrained-random testing, and coverage-driven verification, and more recently methodologies such as Universal Verification Methodology (UVM) are being used.  These methodologies, along with languages such as SystemVerilog and Cadence e, help automate the process and provide improved automation and visibility of the verification process.

HW/SW Co-verification

Historically, hardware was tested and verified separately from the software, and any integration testing was not performed until very late in the design process.  However, this often leaves many corner cases untested, and lengthens the system integration.  Using fast simulation models and virtual platforms, it is now possible to run what would traditionally be hardware tests using the actual target software.  In addition to providing more test coverage, this allow for testing of the interactions between the hardware and software.

System-level Verification

Consumer electronics and other products are increasingly making use of System-On-a-Chip (SOC) and related technologies.  The hardware blocks, along with simulation models (and other verification IP) are often supplied by a number of different vendors.  This greatly increasing complexity requires significantly increased effort to verify correct operation.